Design and implementation of high-speed signal processing system for 2-D state-space digital filters using distributed arithmetic

Author

Kawamata, Masayuki ; Yamakage, Tomoo

Author_Institution

Fac. of Eng., Tohoku Univ., Sendai, Japan

fYear

1990

fDate

1-3 May 1990

Firstpage

735

Abstract

A high-speed signal processing system for 2-D state-space digital filter is proposed. The architecture of the signal processing system is a linear systolic array. The performance of the system implemented with discrete ICs is evaluated. One processing element of the system consists of 2750 gates and 2.5 kbit ROMs and thus can be integrated into a single LSI chip. The processing time of the system is 10.1 ms for 2-D signals of size 512×512. Thus, the proposed system can process television images in real time

Keywords

computerised picture processing; real-time systems; systolic arrays; television equipment; two-dimensional digital filters; 10.1 ms; 2-D state-space digital filters; 2.5 kbit; discrete ICs; distributed arithmetic; high-speed signal processing system; linear systolic array; process television images in real time; processing time; Array signal processing; Digital filters; Digital signal processing; Large scale integration; Read only memory; Real time systems; Signal design; Signal processing; Systolic arrays; TV;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112184

Filename

112184