DocumentCode
262082
Title
5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor
Author
Grenat, Aaron ; Pant, Sanjay ; Rachala, Ravinder ; Naffziger, Samuel
Author_Institution
AMD, Austin, TX, USA
fYear
2014
fDate
9-13 Feb. 2014
Firstpage
106
Lastpage
107
Abstract
In high-performance microprocessor cores, the on-die supply voltage seen by the transistors is non-ideal and exhibits significant fluctuations. These supply fluctuations are caused by sudden changes in the current consumed by the microprocessor in response to variations in workloads. This non-ideal supply can cause performance degradation or functional failures. Therefore, a significant amount of margin (10-15%) needs to be added to the ideal voltage (if there were no AC voltage variations) to ensure that the processor always executes correctly at the committed voltage-frequency points. This excess voltage wastes power proportional to the square of the voltage increase.
Keywords
microprocessor chips; transistors; AC voltage variation; adaptive clocking system; current consumption; on-die supply voltage fluctuation; size 28 nm; transistor; x86-64 microprocessor core; Adaptive systems; Clocks; Microprocessors; Phase locked loops; Program processors; Synchronization; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4799-0918-6
Type
conf
DOI
10.1109/ISSCC.2014.6757358
Filename
6757358
Link To Document