6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters

Data converters are required to interface digital processing engines, for example FPGAs, to the real world. Data conversion is typically accomplished using discrete devices that are interfaced to the FPGA using various IO standards. However, exponential growth in bandwidth as a result of increasing channel count and higher sample rate means this IO interface is becoming a limiting factor in the system budget with respect to interconnect complexity and associated power. The integration of flexible data converters with FPGA eliminates this IO cost and also offers a dynamically scalable, power efficient platform solution that addresses diverse application needs. In this paper, we demonstrate an aggregate bandwidth in excess of 400Gb/s using sixteen 16b DAC instances running at 1.6GS/s with an FPGA-to-die interface power of 0.3mW/Gb/s. We introduce a reconfigurable receive system that allows channel count to trade with system sample rate. Specifically, we demonstrate a 500MS/s ADC by interleaving four 125MS/s units.