Title :
Performance driven analog layout compiler
Author :
Hong, Seong K. ; Allen, Phillip E.
Author_Institution :
Dept. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
An approach to developing an automated analog layout compiler which results in a circuit layout based on a user-specified performance is described. The final layout is derived from sensitivities of the circuit performance with respect to layout interconnect parasitics and recognition rules of various configurations and topologies. The parasitic effects, which are important from an analog layout point of view, are minimized by this approach. This methodology is currently implemented in an analog circuit layout compiler
Keywords :
analogue circuits; circuit layout CAD; network topology; sensitivity analysis; analog layout compiler; circuit layout; circuit performance; configurations; layout interconnect parasitics; parasitic effects; recognition rules; sensitivities; topologies; user-specified performance; Analog circuits; Circuit optimization; Circuit topology; Differential amplifiers; Integrated circuit interconnections; Integrated circuit layout; Mirrors; Routing; SPICE; Sensitivity analysis;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112214
