Design methodology for analog VLSI with over 10000 elements

Analog VLSI CAD is described from the practical point of view. The problems associated with analog IC design are discussed. These problems are classified as the circuit design problems and layout design problems. During the circuit design process, various constraints are produced for the layout design. Moreover layout design itself contains some constraints. Therefore, the layout design cannot be performed separately from the circuit design. Because the integration scale of analog LSIs is too large for layout to be done all at once, a hierarchical design method must be introduced. Circuit simulation for analog VLSI also contains some problems. Simulation time is too long to evaluate the whole circuit. Therefore, an efficient method must be introduced for circuit simulation also. The method has to incorporate expert knowledge. Consequently, a knowledge database must be introduced to make analog VLSI CAD practical. CAI for the analog circuit engineer is also desirable