History-Based Dynamic Voltage Scaling with Few Number of Voltage Modes for GALS NoC

Author

Rahimi, Abbas ; Salehi, Mostafa E. ; Fattah, Mohammad ; Mohammadi, Siamak

Author_Institution

Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran

fYear

2010

fDate

21-23 May 2010

Firstpage

1

Lastpage

6

Abstract

In this paper, we propose a history-based dynamic voltage scaling (DVS) scheme for a GALS NoC which is suitable for MPSoC architectures. The DVS scheme exploits the link utilization and adjusts the router voltages among few number of voltage modes. The introduced architecture is simulated in 90nm CMOS technology with accurate Spice simulations. Experimental results show that history-based DVS successfully adjusts router voltages to track actual link utilization over time. In comparison to the system in which the voltage is fixed at 1.0v, in a 91% saturated network, the proposed DVS scheme saves dynamic and leakage power about 3.3 and 2.3 times, respectively. In addition, 17% energy-delay saving is achieved in the same traffic load.

Keywords

CMOS integrated circuits; network-on-chip; power aware computing; 90nm CMOS technology; GALS NoC; MPSoC architectures; history-based dynamic voltage scaling; CMOS technology; Clocks; Dynamic voltage scaling; Energy consumption; Frequency; Network-on-a-chip; Power dissipation; Throughput; Timing; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Future Information Technology (FutureTech), 2010 5th International Conference on

Conference_Location

Busan

Print_ISBN

978-1-4244-6948-2

Type

conf

DOI

10.1109/FUTURETECH.2010.5482684

Filename

5482684