Timing-driven placement for general cell layout

A hierarchical technique is presented for the timing-driven placement of the general cells. It is assumed that maximum interconnection delays for nets are given. These timing constraints are transformed to net length constraints using technology-and process-dependent parameters, circuit-specific data such as input capacitance and output drivability, and the structural description, of the circuit. The problem is divided into a bottom-up clustering phase and a top-down enumerative placement phase. Both the natural connectivities and the net length constraints are considered during the bottom-up phase in order to generate a hierarchical cluster tree. During the top-down placement phase, they place each node of the cluster tree so that the layout area and total interconnection length are minimized while satisfying the net length constraints