Performance-driven layout of CMOS VLSI circuits

As design rules get scaled down to submicron dimensions, physical CAD tools need to be much more performance-driven as opposed to purely geometry-driven. For instance, to help prevent timing bottlenecks, it is necessary to consider timing-critical nets during circuit partitioning, placement, and routing phases. Long parallel lines can cause crosstalk problems; therefore, it is prudent to limit the length of parallel runners, especially in high-speed circuit layout. The issues are even more complex in active circuit layout. For sensitive analog circuits or clock distribution circuits, various symmetry constraints need to be met. Recent developments in performance-driven layout techniques are reviewed, and these newly emerging issues are discussed