DocumentCode :
2621479
Title :
Synthesis for high performance random logic layout
Author :
Rose, M. ; Papakonstantinou, N. ; Wellington, G. ; Kirkpatrick, D. ; Wiesel, M.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
fYear :
1990
fDate :
1-3 May 1990
Firstpage :
885
Abstract :
Techniques are described which are used by Intel´s standard cell place and route system to achieve dense, high-performance results. The system uses a two-step approach to achieve high performance: first reduce the average path length by producing a dense result, and then adjust the result to reduce delay on the slowest paths. The performance improvement process involves interaction between the layout tool and some of Intel´s performance verification tools
Keywords :
cellular arrays; circuit layout CAD; logic CAD; Intel; delay; high performance random logic layout; layout tool; path length; performance verification tools; place and route system; slowest paths; standard cell; two-step approach; Application specific integrated circuits; Automatic control; Automation; Control system synthesis; Data mining; Delay; Geometry; Logic; Packaging; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
Type :
conf
DOI :
10.1109/ISCAS.1990.112230
Filename :
112230
Link To Document :
بازگشت