A CMOS high-speed front-end for cluster counting techniques in ionization detectors

The counting of the consecutive ionization clusters in a drift chamber is a very promising technique for particle identification purposes. Although this technique features a number of advantages, the bottleneck for its implementation is represented by the difficulties in realizing a low cost, high-speed electronic interface. In fact, typical time separation between each ionization act in a helium-based gas mixture is from a few ns to a few tens of ns. Thus the read-out interface has to be able to process such a high-speed signals. It will be demonstrated that a read-out channel composed of a fast, large bandwidth preamplifier and of a large conversion rate Analog-to-Digital converter fullfil all the requirements for cluster counting. The recent scaled CMOS integrated circuit technologies allows to realize such a low-cost high-speed front-end, opening the possibility of realizing efficient cluster-counter-based detectors. In this paper, a CMOS 0.13 mum integrated readout circuit, including a fast preamplifier (with a -3B bandwidth of 500 MHz) and lGS/s-6bit ADC is designed for the central tracker of a future collider (ILC, super-B). The performance and the design issues associated to this architecture are discussed.