Title :
10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications
Author :
Saint-Laurent, Martin ; Bassett, Paul ; Ken Lin ; Yuhe Wang ; Son Le ; Xufeng Chen ; Alradaideh, Maen ; Wernimont, Tom ; Ayyar, Kartik ; Bui, Dan ; Galbi, Dwight ; Lester, Allan ; Anderson, Willie
Author_Institution :
Qualcomm, Austin, TX, USA
Abstract :
A very-long instruction word (VLIW) Hexagon™ DSP is fabricated using a 28 nm high-κ metal-gate process technology optimized for mobile applications [1]. The DSP is designed for a heterogeneous computing environment. It targets high performance and low power across a wide variety of multimedia and modem applications, under aggressive area targets. Its architecture pursues high IPC as opposed to high frequency [2]. It includes a 32 kB L1 data cache (D$), a 16 kB L1 instruction cache (I$), and a 256 kB L2 cache.
Keywords :
cache storage; digital signal processing chips; high-k dielectric thin films; low-power electronics; voltage regulators; L1 data cache; L1 instruction cache; L2 cache; VLIW; aggressive area targets; energy-efficient mobile applications; heterogeneous computing environment; high IPC; high-κ metal-gate process technology; high-performance mobile applications; modem applications; on-chip LDO; size 28 nm; storage capacity 16 Kbit; storage capacity 256 Kbit; storage capacity 32 Kbit; very-long instruction word Hexagon DSP; Arrays; Clocks; Digital signal processing; Logic gates; Mobile communication; Synchronization; System-on-chip;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-0918-6
DOI :
10.1109/ISSCC.2014.6757388
