New developments for CMOS SSPMs

A high fill factor SSPM built using a standard CMOS fabrication process can provide an energy resolution of 12.4% at 511 keV using CsI(Tl) crystals. The SSPM was operated at an excess bias of 2 V and 0 °C. The magnitude of the noise terms of the SSPM under these conditions are provided. This is compared to the energy resolution of 11.7% using a PMT at room temperature and the identical crystal. CMOS SSPMs can provide PMT-like energy resolution. Additional developments in back-illuminated and position-sensitive SSPMs devices are provided. A back-illuminated device has the promise of a low-noise, high fill-factor design, and the initial results of the quantum efficiency of back-illuminated, thinned devices, fabricated with an existing SSPM design, are provided. For position-sensitive SSPMs, an image of a 3 × 3 CsI array has been made with an SSPM based on a resistive-network configuration to provide position information has been made with minimal distortions.