11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR

Pipeline ADCs have traditionally served as a general-purpose architecture for high-speed and high-resolution applications such as medical and wireless receivers. Recently, achieving the highest levels of linearity with ultra-low power consumption has proven to be extremely challenging using modern CMOS technology with limited headroom. While zero-crossing-based circuits (ZCBC) have proven to be a power-efficient alternative to opamps in pipeline ADCs, performance using zero-crossing techniques have to-date only been demonstrated with ENOB ≤11. This paper presents a 15b 48MS/s zero-crossing-based pipeline ADC that achieves low power consumption of 99fJ/step and high linearity performance of 73.1dB SNDR and >80dB SFDR at Nyquist, demonstrating state-of-the-art FoM for thermal-noise-limited designs of 165.1dB.