15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider

Digital phase-locked loops (DPLLs) [1-7] have received considerable attention recently due to their compatibility with advanced CMOS technology. However, there are two critical factors hindering their uptake in SoC products. One factor is that a digitally controlled oscillator (DCO) is highly sensitive to supply noise. A common solution is to apply voltage regulation or to adopt digital calibration [2] at the cost of larger area, higher power consumption or both. The other factor is a power-hungry time-to-digital converter (TDC), which typically requires complex auxiliary circuitry to overcome sensitivity to process, voltage and temperature [3]. A bang-bang phase/frequency detector (BBPFD) is a good alternative to the TDC for low-power small-size applications. A fractional-N implementation, however, still demands a fractional frequency divider with high design complexity [5]. This paper presents a bang-bang all-digital fractional-N PLL, which occupies a small area, consumes low power and addresses the aforementioned issues. A block diagram of the fractional-N DPLL is shown in Fig. 15.2.1. An automatic frequency controller (AFC) tunes a DCO frequency in the foreground for fast locking. The DCO employs a supply-noise canceling architecture to address the power supply noise issue with negligible power and area overhead. We adopt a phase-interpolator-based fractional divider controlled by a walking-one phase selector for low power and compactness.