• DocumentCode
    2623106
  • Title

    Do´s and don´ts with the Agilent´s G-Link chipset

  • Author

    Aloisio, Alberto ; Cevenini, Francesco ; Izzo, Vincenzo

  • Author_Institution
    INFN, Sezione di Napoli
  • fYear
    2005
  • fDate
    10-10 June 2005
  • Abstract
    The Agilent´s G-Link serializers-deserializers are long lasting and widely used devices to implement serial links in the range of ~1Gbit/s on copper and fibres. They feature a wide clocking window spanning the 13 to 70 MHz range, the ability to compensate for a constant phase delay in the clock distribution between the Tx and Rx node, low and deterministic link latency. All that makes this old-fashioned, power-hungry bipolar chipset still a popular choice in the design of nowadays trigger and data acquisition systems. The last entry in the family, named HDMP-103xA, has been released in second half of 2001, as a drop-in replacement for the previous HDMP-103x silicon version. Despite the upgrade, the latest G-Link chip-set still suffers from subtle misbehaviors and undocumented bugs which may jeopardize also a very conservative design. In this paper we report our experience with G-Link during the design and test of the optical link for Level-1 Muon Trigger of the ATLAS experiment
  • Keywords
    microprocessor chips; Agilent G-Link chipset; Level-1 Muon Trigger; data acquisition; jitter; noise generators; phase locked loop; serial links; serializers-deserializers; Clocks; Computer bugs; Copper; Data acquisition; Delay; Optical design; Optical fiber communication; Optical fiber devices; Silicon; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Real Time Conference, 2005. 14th IEEE-NPSS
  • Conference_Location
    Stockholm
  • Print_ISBN
    0-7803-9183-7
  • Type

    conf

  • DOI
    10.1109/RTC.2005.1547483
  • Filename
    1547483