DocumentCode :
2623212
Title :
On Minimization of Peak Power for Scan Circuit during Test
Author :
Tudu, Jaynarayan T. ; Larsson, Erik ; Singh, Virendra ; Agrawal, Vishwani D.
Author_Institution :
Indian Inst. of Sci., Bangalore, India
fYear :
2009
fDate :
25-29 May 2009
Firstpage :
25
Lastpage :
30
Abstract :
Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power, below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%.
Keywords :
circuit testing; graph theory; low-power electronics; vectors; graph theory; minimum peak power; scan circuit; switching activity; test vector re-ordering; Circuit testing; Current supplies; Frequency; Minimization; Power dissipation; Power supplies; Scheduling; Sequential analysis; Switching circuits; Test pattern generators; Low power test; Peak Power; Power droop; Test vector re-ordering;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2009 14th IEEE European
Conference_Location :
Seville
Print_ISBN :
978-0-7695-3703-0
Type :
conf
DOI :
10.1109/ETS.2009.36
Filename :
5170455
Link To Document :
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