The development of a hardware abstraction layer generator for system-on-chip functional verification

Nowadays functional verification of large system-on-chip has taken about 70% to 80% of the total design effort. The large amount of IP´s of current SoC´s makes the work of verification engineers quite hard due to the need to guarantee that the design is bug free before it is sent to tape out. In order to reduce the time spent in the functional verification and support the verification engineers, this work proposes a Hardware Abstract Layer (HAL) generator. The HAL generator is part of a methodology for SoC functional verification, which is supported by IP-XACT and aims to automate the functional verification flow. The HAL generator is able for creating C functions that allow the manipulation of registers and their fields at a very high abstraction level allowing the verification engineers to write their test cases without need to worrying about masks, macros, define and/or pointers manipulation.