An efficient hardware design for rejecting common mode in a group of adjacent channels of silicon microstrip sensors used in high energy physics experiments

Algorithms have been studied using Monte Carlo techniques and implemented in a fast Xilinx Virtex II pro FPGA, in order to calculate and remove after pedestal subtraction the common mode of a group of adjacent channels. The implementation of the algorithms has been optimized both for speed and minimal FPGA resources, in order to be used in multi-channel applications. This work has been carried out in order to define the optimum algorithm for common mode calculation to be implemented for common mode rejection in the CMS preshower detector