DocumentCode
2623312
Title
FPGA implementation of a greedy algorithm for set covering
Author
Aloisio, Alberto ; Izzo, Vincenzo ; Rampone, Salvatore
Author_Institution
Dipt. di Sci. Fisiche, Universita di Napoli "Federico II"
fYear
2005
fDate
10-10 June 2005
Abstract
A version of a new greedy algorithm for approximating minimum set cover is presented. The algorithm, while not randomized, is based on a probability distribution that leads the greedy choice. The algorithm has been specifically tailored to run on platforms with minimal computational hardware. We also describe an implementation based on a FPGA which makes the algorithm suitable for embedded and real-time architectures
Keywords
digital arithmetic; embedded systems; field programmable gate arrays; greedy algorithms; FPGA; embedded architecture; greedy algorithm; minimum set cover approximation; real-time architecture; Approximation algorithms; Computer architecture; Field programmable gate arrays; Greedy algorithms; Hardware; Helium; Heuristic algorithms; Polynomials; Probability distribution; Wireless networks;
fLanguage
English
Publisher
ieee
Conference_Titel
Real Time Conference, 2005. 14th IEEE-NPSS
Conference_Location
Stockholm
Print_ISBN
0-7803-9183-7
Type
conf
DOI
10.1109/RTC.2005.1547493
Filename
1547493
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