PLL noise reduction circuit to stabilize the disturbed clock pulse due to noise

This study is about the method of obtaining stable clock pulse against incident noise by applying a PLL (phase locked loop) noise reduction circuit which the authors propose. In the proposed circuit, clock pulse is distributed without timing-skew by distributing common reference voltage to the voltage comparators included in the PLL noise reduction circuits. Further, stable clock pulse against large incident noise is realized by adding to PLL both a low-pass-filter with two different kinds of bandwidth and an edge detector of the phase variation caused by noise