• DocumentCode
    262363
  • Title

    19.2 A 93.4mm2 64Gb MLC NAND-flash memory with 16nm CMOS technology

  • Author

    Sungdae Choi ; Duckju Kim ; Sungwook Choi ; Byungryul Kim ; Sunghyun Jung ; Kichang Chun ; Namkyeong Kim ; Wanseob Lee ; Taisik Shin ; Hyunjong Jin ; Hyunchul Cho ; Sunghoon Ahn ; Yonghwan Hong ; Ingon Yang ; Byoungyoung Kim ; Pilseon Yoo ; Youngdon Jung

  • Author_Institution
    SK Hynix, Icheon, South Korea
  • fYear
    2014
  • fDate
    9-13 Feb. 2014
  • Firstpage
    328
  • Lastpage
    329
  • Abstract
    This paper presents a 64Gb MLC NAND-Flash memory fabricated with 16nm CMOS process technology to achieve high density and as small as 93.4mm2 die area. The chip consists of two planes of 1072 blocks each. A block consists of a string with 128 cells and a page size with 16KB and spare area for error-correction coding (ECC), totaling 4MB of capacity. The chip supports negative-level wordline drivability to increase cell Vth margin.
  • Keywords
    CMOS memory circuits; NAND circuits; error correction codes; flash memories; logic testing; CMOS process technology; ECC; MLC NAND-flash memory; error-correction coding; size 16 nm; Computer architecture; Couplings; Flash memories; Integrated circuit interconnections; Microprocessors; Noise; Sensors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4799-0918-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.2014.6757455
  • Filename
    6757455
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=262363