An advanced interlock solution for TTF2/XFEL RF stations

The main task of the interlock system is to prevent any damage from the cost expensive components of the RF station. The implementation of the interlock should guarantee a maximum uninterrupted time of operation which implies the implementation of self diagnostic and repair strategies on module basis. Additional tasks include collection and temporary storage of status information of individual channels; transfer of this information to a higher level control system, but also the implementation of slow control functions. The interlock implementation is based on a 4U 19"-crate which houses a controller and different slave modules implementing the interface to the components of the RF station. A dedicated, user defined backplane connects the controller to all slave modules. The controller incorporates the 32-bit RISC NIOS-II processor inside a Cyclone FPGA device. The program running on this processor performs all necessary control and monitoring functions to all slave modules in the crate, but not the interlock function itself. The interlock function is implemented in pure hardware and functions even if the processor stops or the program hangs up. The interface to the higher level control system (DOOCS) is implemented based on a TINE server implementation. In addition, a Web server was developed which provides the possibility to reconfigure the whole FPGA design or to upload a new software version via Ethernet