Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures

Cryptographic algorithms utilize finite-field arithmetic operations in their computations. Due to the constraints of the nodes which benefit from the security and privacy advantages of these algorithms in sensitive applications, these algorithms need to be lightweight. One of the well-known bases used in sensitive computations is dual basis (DB). In this brief, we present low-complexity superserial architectures for the DB multiplication over GF(2^m). To the best of our knowledge, this is the first time that such a multiplier is proposed in the open literature. We have performed complexity analysis for the proposed lightweight architectures, and the results show that the hardware complexity of the proposed superserial multiplier is reduced compared with that of regular serial multipliers. This has been also confirmed through our application-specific integrated circuit hardware- and time-equivalent estimations. The proposed superserial architecture is a step forward toward efficient and lightweight cryptographic algorithms and is suitable for constrained implementations of cryptographic primitives in applications such as smart cards, handheld devices, life-critical wearable and implantable medical devices, and constrained nodes in the blooming notion of Internet of nano-Things.