Transformation-based peak power reduction for test sequences

Author

Corno, Fulvio ; Rebaudengo, Maurizio ; Sonza Reorda, M. ; Violante, M.

Author_Institution

Dipt. di Autom. e Inf., Politecnico di Torino

fYear

1999

fDate

4-5 Mar 1999

Firstpage

78

Lastpage

83

Abstract

This paper describes a new algorithm for transforming an existing test sequence for sequential circuits into a cheaper one from the point of view of peak power consumption. The algorithm exploits both symbolic techniques (to identify sub-sequences performing a given state transition) and heuristic methods. Preliminary experimental results show that the algorithm is able to reduce the peak power consumption of ATPG-generated sequences by up to 54%, while the reduction of the fault coverage is limited to at most 1%

Keywords

automatic test pattern generation; fault diagnosis; logic testing; sequential circuits; symbol manipulation; ATPG-generated sequences; fault coverage; heuristic methods; sequential circuits; state transition; symbolic techniques; test sequences; transformation-based peak power reduction; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Clocks; Computational modeling; Energy consumption; Power generation; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Low-Power Design, 1999. Proceedings. IEEE Alessandro Volta Memorial Workshop on

Conference_Location

Como

Print_ISBN

0-7695-0019-6

Type

conf

DOI

10.1109/LPD.1999.750406

Filename

750406