• DocumentCode
    262401
  • Title

    20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput

  • Author

    Ming He ; Winoto, Renaldi ; Xiang Gao ; Loeb, Wayne ; Signoff, David ; Wai Lau ; Yuan Lu ; Donghong Cui ; Kun-Seok Lee ; Sai-Wang Tam ; Godoy, Philip ; Yung Chen ; Sanghoon Joo ; Hu, Chuanmin ; Paramanandam, Arvind Anumula ; Xiaoyue Wang ; Chi-Hung Lin ;

  • Author_Institution
    Marvell, Santa Clara, CA, USA
  • fYear
    2014
  • fDate
    9-13 Feb. 2014
  • Firstpage
    350
  • Lastpage
    351
  • Abstract
    The steep growth of digital-content consumption and increasing reliance on wireless networks has resulted in emerging standards such as IEEE 802.11ac. By employing spatial diversity, Multi-user MIMO and high-density modulation (up to 256-QAM), 802.11ac MIMO radios can provide significantly increased throughput, link robustness, and range while maintaining backward-compatibilities with existing 802.11a/n WLAN [1]. However, wide signal bandwidth and high-density modulation lead to significant challenges in all aspects of RF transceiver design, compared to previous WLAN standards. This paper introduces a fully integrated 3-stream MIMO WLAN SoC that integrates all of the functions of an 802.11a/b/g/n/ac WLAN with a record over-the-air TCP/IP throughput of 1.1Gb/s. The 40nm CMOS SoC integrates dual-band (2.4GHz and 5GHz) RF transceivers, data converters, digital physical layer, media access controller, and a PCI Express Gen-2 interface. The RF transceiver employs an all-digital fractional-N PLL with a record Figure-of-Merit (FoM) of -244dB, a wideband low-impedance bias circuit that minimizes pre-PA driver memory effect for 80MHz signal bandwidth, a dual-band receiver with 3dB/4.3dB NF, and a 5th-order Chebyshev low-pass filter with constant-Gm bias and pre-distorted filter coefficients to support up to 80MHz signal bandwidth.
  • Keywords
    CMOS integrated circuits; MIMO communication; UHF integrated circuits; digital phase locked loops; field effect MMIC; radio transceivers; system-on-chip; transport protocols; wireless LAN; 5th-order Chebyshev low-pass filter; CMOS SoC; FoM; PCI Express Gen-2 interface; all-digital fractional-N PLL; bandwidth 80 MHz; bit rate 1.1 Gbit/s; constant-Gm bias; data converters; digital physical layer; digital-content consumption; dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC; dual-band RF transceiver design; figure-of-merit; frequency 2.4 GHz; frequency 5 GHz; fully integrated 3-stream MIMO WLAN SoC; high-density modulation; link robustness; media access controller; multiuser MIMO; over-the-air TCP/IP throughput; pre-PA driver memory effect; pre-distorted filter coefficients; signal bandwidth; size 40 nm; spatial diversity; steep growth; wideband low-impedance bias circuit; wireless networks; Bandwidth; Content management; Digital systems; Filters; MIMO; OFDM; Wireless LAN; Wireless networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4799-0918-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.2014.6757465
  • Filename
    6757465