An efficient hardware implementation for H.264 binary arithmetic encoder

Binary arithmetic coding (BAC) is among the techniques used in H.264 video coding standard to improve the coding efficiency. BAC includes an iterative process of renormalization with up to seven iterations for coding each symbol. Since BAC is also a computational intensive unit in H.264 encoder, various hardware realizations have been proposed for it in the literature. In this paper, we propose a hardware implementation for BAC, which uses lookup table to avoid the iterative coding process and achieves coding rate of one symbol per clock at 260 MHz clock rate. Post synthesize simulation results indicate that the proposed architecture is a resource and speed efficient hardware for H.264 binary arithmetic encoder.