DocumentCode
2624363
Title
Balancing SoC Design and Technology Challenges at 45nm
Author
Stork, J.M.C.
Author_Institution
Texas Instruments, Inc., Dallas, TX
fYear
0
fDate
0-0 0
Firstpage
1
Lastpage
2
Abstract
The ability of advanced CMOS to integrate processor cores, memory and ASIC logic with RF and analog functions on the same die, has enabled unprecedented density and performance especially for mobile communication systems. Continuing this progress at 45nm and below requires simultaneously improving gate density, system power, and functional performance while reducing the cost per finished die
Keywords
CMOS integrated circuits; integrated circuit design; system-on-chip; 45 nm; ASIC logic; RF functions; advanced CMOS integrated circuit; analog functions; balancing SoC design; integrated circuit design; memory circuit; mobile communication systems; processor cores integration; technology challenges; CMOS technology; Cost function; Design optimization; Dielectrics; Energy management; Low voltage; Power system interconnection; Radio frequency; Random access memory; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
1-4244-0005-8
Type
conf
DOI
10.1109/VLSIT.2006.1705188
Filename
1705188
Link To Document