A 60nm NOR Flash Memory Cell Technology Utilizing Back Bias Assisted Band-to-Band Tunneling Induced Hot-Electron Injection (B4-Flash)

Author

Shukuri, Shoji ; Ajika, Natsuo ; Mihara, Masaaki ; Kobayashi, Kazuo ; Endoh, Tetsuo ; Nakashima, Moriyoshi

Author_Institution

GENUSION, Inc., Hyogo

fYear

0

fDate

0-0 0

Firstpage

15

Lastpage

16

Abstract

A p-channel SONOS flash memory cell technology, which provides excellent scalability and high programming efficiency for NOR architecture, has been developed. The cells named B4-Flash utilizing novel back bias assisted band-to-band tunneling induced hot-electron (B4-HE) injection is proposed. By applying a moderate back bias to the cell during programming, the bit-line voltage can be reduced below the supply voltage, 1.8V. Resulting that the B4-Flash, applicable to NOR architecture, achieves the gate length of 60nm, for the first time. Basic operation of the 50nm B4-Flash cell is also confirmed. Proposed B4-HE injection scheme realizes not only extreme scalability but also high programming efficiency for NOR type cell

Keywords

NOR circuits; flash memories; hot carriers; tunnelling; 1.8 V; 50 nm; 60 nm; B4-Flash; NOR architecture; NOR flash memory cell technology; back bias assisted band-to-band tunneling induced hot-electron injection; bit-line voltage; p-channel SONOS technology; programming efficiency; supply voltage; Breakdown voltage; Channel hot electron injection; Flash memory cells; Helium; Low voltage; SONOS devices; Scalability; Secondary generated hot electron injection; Throughput; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705194

Filename

1705194