Title :
Multi-Level NAND Flash Memory with 63 nm-Node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure
Author :
Lee, Chang-Hyun ; Choi, Jungdal ; Kang, Changseok ; Shin, Yoocheol ; Lee, Jang-Sik ; Sel, Jongsun ; Sim, Jaesung ; Jeon, Sanghun ; Choe, Byeong-In ; Bae, Dukwon ; Park, Kitae ; Kim, Kinam
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co. Ltd., Yongin
Abstract :
For the first time, multi-level NAND flash memories with a 63 nm design rule are developed successfully using charge trapping memory cells of Si/SiO2/SiN/Al2O3/TaN (TANOS). We successfully integrated TANOS cells into multi-gigabit multi-level NAND flash memory without changing the memory window and circuit design of the conventional floating-gate type NAND flash memories by improving erase speed. The evolved TANOS cells show four-level cell distribution which is free from program disturbance and a charge loss of less than 0.4 V at high temperature bake test
Keywords :
NAND circuits; electron traps; flash memories; sapphire; silicon; silicon compounds; tantalum compounds; 63 nm; Si-SiO2-SiN-Al2O3-TaN; charge trapping memory cells; erase speed; floating-gate; high temperature bake test; memory window; multi-level NAND flash memories; Circuit synthesis; Circuit testing; Electron traps; Flash memory; Interference; Nonvolatile memory; Research and development; Silicon compounds; Temperature distribution; Threshold voltage;
Conference_Titel :
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0005-8
DOI :
10.1109/VLSIT.2006.1705197
