Observations of single-event upsets and multiple-bit upsets in random access memories on-board the Algerian satellite

In-orbit observations of single-event upset (SEU) and multiple-bit upset (MBU) activity in commercial memories onboard the first Algerian microsatellite Alsat-1, are presented for the Satellite On-Board Computer (SOBC386). The SOBC is an Intel 80C386EX based system that plays a dual role for Alsat-1, acting as the key component of the payload computer as well as the command and control computer for the microsatellite. This paper presents an analysis of the SEU and MBU performance of the memory devices in a low earth orbit, and shows that the typical SEU rate at Alsat-1’s orbit is one error bit in one million bits per day, where 80% of these SEUs cause single-bit errors and the remaining SEUs result in double-bit and multiple-bit errors. This paper presents also the application of the quasi-cyclic codes for memory errors detection and correction (EDAC). In this application, a simple method of decoding is adopted that allows considerable simplification of the EDAC device with a low complexity. The performance of the proposed EDAC is measured and compared with two different EDAC devices, using the same FPGA technology. It is shown that such a technique is very efficient to detect and correct double-bit errors.