Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

Author

Sung-Woong Chung ; Sang-Don Lee ; Se-Aug Jang ; Min-Soo Yoo ; Kwang-Ok Kim ; Chai-O Chung ; Sung Yoon Cho ; Heung-Jae Cho ; Lae-Hee Lee ; Sun-Hwan Hwang ; Jin-Soo Kim ; Bong-Hoon Lee ; Hyo Geun Yoon ; Hyung-Soon Park ; Seung-Joo Baek ; Yun-Seok Cho ; Noh-

fYear

2006

fDate

13-15 June 2006

Firstpage

32

Lastpage

33

Abstract

Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dry-etching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology

Keywords

DRAM chips; MOSFET; 50 nm; DRAM; FinFET; dry etching; highly scalable saddle-fin transistor; recess channel array transistor; Controllability; Doping; Etching; FinFETs; Moon; Random access memory; Research and development; Silicon; Threshold voltage; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705202

Filename

1705202