DocumentCode :
2624702
Title :
A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique
Author :
Yoshida, Makoto ; Kahng, Jaerok ; Lee, Chul ; Jang, Se-Myeong ; Sung, Hyunju ; Kim, Keunnam ; Kim, Hui-Jung ; Jung, Kyoung-Ho ; Yang, Wouns ; Park, Donggun ; Ryu, Byung-Il
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co., Yongin
fYear :
0
fDate :
0-0 0
Firstpage :
34
Lastpage :
35
Abstract :
A full FinFET DRAM core which consists of McFETs for both the sense amplifiers and the sub-word drivers, as well as FinFETs for the memory cell array has been developed. It will efficiently shrink chip size and improve chip performance, and therefore, meet requirements for the future DRAMs with 55nm or smaller design rule. Newly developed schemes which are a selective STT SiN liner removal process, a selective TiN gate stack and narrow active pitch patterning have been successfully integrated
Keywords :
DRAM chips; MOS memory circuits; silicon compounds; DRAM; FinFET; SiN; core integration technology; memory cell array; simple selective fin formation; Circuits; Etching; FinFETs; Metallization; Random access memory; Silicon compounds; Space technology; Threshold voltage; Tin; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0005-8
Type :
conf
DOI :
10.1109/VLSIT.2006.1705203
Filename :
1705203
Link To Document :
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