24.4 A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction

Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1μW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.