A 4-Bit Double SONOS Memory (DSM) with 4 Storage Nodes per Cell for Ultimate Multi-Bit Operation

Author

Oh, Chang Woo ; Kim, Sung Hwan ; Kim, Na Young ; Choi, Yong Lack ; Lee, Kwan Heum ; Kim, Byeong Soo ; Cho, Nam Myun ; Kim, Seung Beom ; Kim, Dong-Won ; Park, Donggun ; Ryu, Byung-Il

Author_Institution

Device Res. Team, Samsung Electron. Co., Yongin

fYear

0

fDate

0-0 0

Firstpage

40

Lastpage

41

Abstract

We proposed a 4-bit double SONOS memory with two ONO layers, 4 storage nodes, for ultimate multi-bit operation and firstly demonstrate 4-bit operation using the physically separated 4 storage nodes. By using CHEI/HHI program/erase, each node was easily programmed and erased without any detrimental interference among the nodes. In the gate length of 120nm, the read/write margins of ~0.8V for front side (FS) and ~1.1V for back side (BS) at V_DS=1.2V was obtained. The V_TH shifts of ~1.5V for both program/erase (P/E) were observed with the P/E conditions, V_D/V_FG=3/5V, 3/-4V for FS and VD/VBG=3.2/7V, 3.2/-5V for BS, respectively, with the duration of 1 ms. The V_TH windows of ~0.9V for FS and ~1.1V for BS were achieved even after 10⁴ P/E cycles

Keywords

integrated memory circuits; 1 ms; 4 bit; double SONOS memory; storage nodes; ultimate multi bit operation; Channel hot electron injection; Electron traps; Fabrication; Germanium silicon alloys; Hot carriers; Interference; Nonvolatile memory; Research and development; SONOS devices; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705206

Filename

1705206