Sub-5nm All-Around Gate FinFET for Ultimate Scaling

Author

Lee, Hyunjin ; Yu, Lee-eun ; Ryu, Seong-Wan ; Han, Jin-Woo ; Jeon, Kanghoon ; Jang, Dong-Yoon ; Kim, Kuk-Hwan ; Lee, Jiye ; Kim, Ju-Hyun ; Jeon, Sang Cheol ; Lee, Gi Seong ; Oh, Jae Sub ; Park, Yun Chang ; Bae, Woo Ho ; Lee, Hee Mok ; Yang, Jun Mo ; Yoo,

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon

fYear

0

fDate

0-0 0

Firstpage

58

Lastpage

59

Abstract

Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO₂ shows an I_Dsat of 497muA/mum at V_G=V _D=1.0V. Characteristics of sub-5nm transistor are verified by using 3-D simulations as well as analytical models. A threshold voltage increases as the fin width reduces by quantum confinement effects. The threshold voltage shift was fitted to a theoretical model with consideration of the first-order perturbation theory. And a channel orientation effect, based on a current-flow direction, is shown

Keywords

MOSFET; nanotechnology; semiconductor device models; 1.4 nm; 3 nm; 3D simulations; HfO₂; all-around gate FinFET; channel orientation effect; current flow direction; first-order perturbation theory; quantum confinement effects; Analytical models; Annealing; Etching; FinFETs; Hafnium oxide; Lithography; Optical films; Potential well; Scalability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705215

Filename

1705215