Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

Author

Chen, Xia ; Fang, Shao-Yun ; Gao, Wenzhong ; Dyer, T. ; Teh, Y.W. ; Tan, S.S. ; Ko, Y. ; Baiocco, C. ; Ajmera, A. ; Park, Jongho ; Kim, Jung-Ho ; Stierstorfer, R. ; Chidambarrao, D. ; Luo, Zhengqian ; Nivo, N. ; Nguyen, P. ; Yuan, Jiaxin ; Panda, Siddhart

Author_Institution

IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY

fYear

0

fDate

0-0 0

Firstpage

60

Lastpage

61

Abstract

Integration of stress proximity technique (SPT) and dual stress liners (DSL) has been demonstrated for the first time. The proximity of stress liner is enhanced by spacer removal after salicidation and before the DSL process. It maximizes the strain transfer from nitride liner to the channel. PFET drive current improvements of 20% for isolated and 28% for nested poly gate pitch devices have been achieved with SPT. Leading edge PFET I_on=660muA/mum at I_off=100nA/mum at 1V V_dd operation is demonstrated without using embedded SiGe junctions. Inverter ring oscillator delay is reduced by 15% with SPT

Keywords

Ge-Si alloys; MOSFET; nanotechnology; 1 V; 45 nm; PFET; SiGe; dual stress liner; inverter ring oscillator delay; poly gate pitch devices; salicidation; semiconductor junctions; stress proximity technique; Capacitive sensors; Compressive stress; DSL; Germanium silicon alloys; Research and development; Semiconductor device manufacture; Silicon germanium; Space technology; Surface-mount technology; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705216

Filename

1705216