Title :
Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond
Author :
Kawasaki, H. ; Okano, K. ; Kaneko, A. ; Yagishita, A. ; Izumida, T. ; Kanemura, T. ; Kasai, K. ; Ishida, T. ; Sasaki, T. ; Takeyama, Y. ; Aoki, N. ; Ohtsuka, N. ; Suguro, K. ; Eguchi, K. ; Tsunashima, Y. ; Inaba, S. ; Ishimaru, K. ; Ishiuchi, H.
Author_Institution :
SoC R&D Center & Process & Manuf. Eng. Center, Toshiba Corp. Semicond. Co., Yokohama
Abstract :
Integration schemes of bulk FinFET SRAM cell with bulk planar FET peripheral circuit are studied for the first time. Two types of SRAM cells with different beta-ratio were fabricated and investigated in the view of static noise margin (SNM). High SNM of 122 mV is obtained in the cell with 15 nm fin width, 90 nm channel height and 20 nm gate length at Vdd = 0.6 V. This is the smallest gate length FinFET SRAM reported to date. A higher beta ratio (beta> 2.0) in FinFET SRAM cell will be also achieved by tuning the effective channel width of each FinFETs without area penalty by taking advantage of bulk-Si substrate
Keywords :
CMOS logic circuits; MOSFET; SRAM chips; 122 mV; 15 nm; 20 nm; 32 nm; 90 nm; FinFET SRAM cell technology; planar FET peripheral circuit; static noise margin; CMOS analog integrated circuits; CMOS technology; Circuit noise; Design optimization; Electrodes; FETs; FinFETs; Impurities; Random access memory; Semiconductor device noise;
Conference_Titel :
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0005-8
DOI :
10.1109/VLSIT.2006.1705221
