High-speed, fixed-latency serial links with FPGAs

Fixed-latency serial links find application in trigger systems of High Energy Physics experiments requiring a predictable data transfer timing. In this work we present an architecture based on high-speed transceivers embedded in the latest generation Field Programmable Gate Arrays. Despite this kind of transceivers do not offer fixed latency by default, we developed a configuration and a clocking scheme to achieve it. The ATLAS Experiment level-one muon trigger is built as a synchronous pipeline and includes some fixed-latency serial links to transfer data from the detector to the counting room. The links are based on Agilent G-Link, whose production discontinued and no compatible off-the-shelf chip-sets are available. In order to have a replacement solution for G-Link-based links, we decided to adopt its protocol.