NiSi Schottky Barrier Process-Strained Si (SB-PSS) CMOS Technology for High Performance Applications

Author

Ko, C.H. ; Chen, H.W. ; Wang, T.J. ; Kuan, T.M. ; Hsu, J.W. ; Huang, C.Y. ; Ge, C.H. ; Lai, L.-S. ; Lee, W.C.

Author_Institution

Taiwan Semicond. Manuf. Co., Ltd., Hsinchu

fYear

0

fDate

0-0 0

Firstpage

80

Lastpage

81

Abstract

State-of-the-art process-strained Si (PSS) technology featuring single-NiSi Schottky source/drain (S/D) and ultra-thin gate oxide of 1.2 nm is demonstrated for L_gate down to 39 nm. +10% performance boost of Schottky-barrier (SB)-PSS NMOS, as compared to its non-Schottky counterpart, is demonstrated due to series resistance reduction of the silicide S/D and enhanced strain effects. Highest SB-PSS PMOS drive current of 821 muA/mum (at V_D = -1.2V and I_off = 100 nA/mum) is recorded when integrated with recessed Si_1-xGe_x S/D stressor

Keywords

MOS integrated circuits; Schottky barriers; nickel compounds; -1.2 V; 1.2 nm; 39 nm; CMOS technology; NMOS; NiSi; PMOS drive current; Schottky barrier process-strained silicon technology; series resistance reduction; ultra-thin gate oxide; CMOS process; CMOS technology; Capacitive sensors; MOS devices; Nickel; Reliability engineering; Schottky barriers; Silicidation; Silicides; Strain control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705226

Filename

1705226