Title :
Novel FUSI Strained Engineering for 45-nm Node CMOS Performance Enhancement
Author :
Lin, C.T. ; Hsu, C.H. ; Chen, L.W. ; Chen, T.F. ; Hsu, C.R. ; Lin, C.H. ; Chiang, Sinclair ; Cho, D.C. ; Tsai, C.T. ; Ma, G.H.
Author_Institution :
Central R&D Div., United Microelectron. Corp., Hsin-Chu
Abstract :
FUSI metal gate with strained engineering is extensively investigated and reported for the first time. Enveloped FUSI (fully silicided) phase transfer and volume change induced stress exhibits 10% NMOS ION enhancement. Further, the second CESL (contact etch stop layer) induced stress raised another 8% NMOS ION gain. Although the first CESL on poly-gate top removed by FUSI CMP leads to 10% PMOS ION degradation, it can be recovered or further improved by a dual CESL process
Keywords :
CMOS integrated circuits; stress analysis; CESL; CMOS performance enhancement; CMP; NMOS; PMOS; contact etch stop layer; fully silicided metal gate; fully silicided phase transfer; fully silicided volume change; strained engineering; Cities and towns; Compressive stress; Degradation; Electrodes; MOS devices; Microelectronics; Research and development; Temperature; Tensile stress; Thermal stresses;
Conference_Titel :
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0005-8
DOI :
10.1109/VLSIT.2006.1705232
