DocumentCode :
262550
Title :
29.1 A 5mW CT ΔΣ ADC with embedded 2nd-order active filter and VGA achieving 82dB DR in 2MHz BW
Author :
Rajan, Radha ; Pavan, Shanthi
Author_Institution :
IIT Madras, Chennai, India
fYear :
2014
fDate :
9-13 Feb. 2014
Firstpage :
478
Lastpage :
479
Abstract :
Conventional continuous-time delta-sigma modulator (CTDSM) architectures do not allow independent control of the shape and bandwidth of the signal transfer function (STF), since the STF is simply a by-product of NTF synthesis. This is particularly troublesome when the input to the CTDSM consists of large out-of-band interferers; handling them without saturating the quantizer needs larger inband DR, leading to increased power dissipation. A solution to this problem is to use a filter upfront to attenuate interferers. Alternatively [1], the filter can be moved into the CTDSM loop. In [1], a 1st-order RC filter was used to “tame” the STF peak of a cascade of integrators with feedforward summation (CIFF) DSM. Apart from the limited selectivity offered by a 1st-order filter, an active feedback path was necessary to stabilize the loop. The CTDSM in our work obtains an STF with a sharper transition band and a lower cutoff frequency (normalized to the desired signal bandwidth) compared to [1], with the aim of more effectively attenuating close-in interferers. This is realized by embedding a 2nd-order active filter into the CTDSM. We show that this has the same functionality as the filter upfront, but achieves better linearity (for the same noise and power dissipation) when compared to the filter-CTDSM cascade. Further, no extra active circuitry is necessary to stabilize the loop. Measurements of a CTDSM (signal BW=2MHz), with a built-in VGA (0 to 18dB) and a 2nd-order Butterworth filter (4MHz cutoff), show that the out-of-band IIP3 improves by about 10dB when compared to the CTDSM with the filter placed upfront. The filtering CTDSM+VGA, which uses a single-bit quantizer and a 4-tap FIR DAC, achieves a DR of 92dB in a 2MHz BW while consuming 5mW in a 0.13μm CMOS process. The peak instantaneous DR/SNR/SNDR are 82/80.5/74.5dB. With the VGA, the DR is 92dB.
Keywords :
Butterworth filters; CMOS digital integrated circuits; RC circuits; analogue-digital conversion; continuous time filters; delta-sigma modulation; transfer functions; 4-tap FIR DAC; CIFF DSM; CMOS process; CT ΔΣ ADC; CTDSM loop; NTF synthesis; STF; active feedback path; bandwidth 2 MHz; built-in VGA; cascade-of-integrator-feedforward summation DSM; continuous-time delta-sigma modulator architecture; cutoff frequency; embedded second-order active filter; filter upfront; filter-CTDSM cascade; first-order RC filter; inband DR; interferer attenuation; loop stabilization; out-of-band IIP3; out-of-band interferers; peak instantaneous DR-SNR-SNDR; power 5 mW; power dissipation; second-order Butterworth filter; signal transfer function; single-bit quantizer; size 0.13 mum; transition band; Bandwidth; Delta-sigma modulation; Feedback; Modulation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
978-1-4799-0918-6
Type :
conf
DOI :
10.1109/ISSCC.2014.6757520
Filename :
6757520
Link To Document :
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