Integration of Self-Formed Barrier Technology for 32nm-Node Cu Dual-Damascene Interconnects with Hybrid Low-k (PAr/SiOC) Structure

Author

Ohoka, Y. ; Inoue, K. ; Hayashi, T. ; Komai, N. ; Arakawa, S. ; Kanamura, R. ; Kadomura, S.

Author_Institution

Semicond. Bus. Unit, Sony Corp., Atsugi

fYear

0

fDate

0-0 0

Firstpage

114

Lastpage

115

Abstract

Self-formed MnO_x barrier technology has been successfully integrated for 150nm pitch Cu dual-damascene interconnects with PAr/SiOC (k=2.65) hybrid structure. Barrier formation at the interface of Cu and various low-k films with few Si or O was confirmed by adhesion, XPS and TEM/EDX analyses. No degradation of interconnect performance and excellent electromigration lifetime were verified. It is concluded that this self-formed barrier technology is a promising technique to satisfy the reliability requirement for 32nm-node Cu/low-k interconnects

Keywords

X-ray chemical analysis; X-ray photoelectron spectra; argon compounds; copper alloys; diffusion barriers; electromigration; integrated circuit interconnections; low-k dielectric thin films; manganese compounds; oxygen compounds; phosphorus compounds; silicon compounds; transmission electron microscopy; 32 nm; Cu; MnO; PAr-SiOC; TEM/EDX analysis; XPS analysis; barrier formation; dual-damascene interconnects; electromigration lifetime; hybrid low-k structure; low-k interconnects; self-formed barrier technology; Adhesives; Annealing; Automatic testing; Degradation; Dielectrics; Electromigration; Peak to average power ratio; Semiconductor films; Silicon; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705243

Filename

1705243