• DocumentCode
    2625606
  • Title

    Lower Resistance Scaled Metal Contacts to Silicide for Advanced CMOS

  • Author

    Topol, A. ; Sheraw, C. ; Wong, Kai-Kit ; Shao, Xingyue ; Knarr, R. ; Rossnagel, S. ; Yang, C.-C. ; Baker-O´Neal, B. ; Simon, A. ; Haran, B. ; Li, Yuhua ; Ouyang, Chunmei ; Allen, S. ; Brodsky, C. ; Cohen, Sholom ; Deligianni, L. ; Chen, Xia ; Deshpande, S

  • Author_Institution
    T.J. Watson Res. Center, IBM Semicond. R&D Center, Yorktown Height, NY
  • fYear
    0
  • fDate
    0-0 0
  • Abstract
    A key challenge for high performance CMOS devices is the external parasitic resistance. This paper addresses scaling trends of contact level and discusses emerging constraints related to the properties of materials used in the current technology. Experimental and theoretical data presented herein are critical in understanding CA challenges beyond the 45 nm technology node and show great potential for copper as the alternative to tungsten process for CA metallization
  • Keywords
    CMOS integrated circuits; integrated circuit metallisation; 45 nm; CA metallization; CMOS; contact level; external parasitic resistance; scaled metal contacts; scaling trends; silicide; CMOS technology; Contact resistance; Copper; Metallization; Nanoscale devices; Plugs; Predictive models; Research and development; Silicides; Tungsten;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    1-4244-0005-8
  • Type

    conf

  • DOI
    10.1109/VLSIT.2006.1705244
  • Filename
    1705244
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2625606