Author :
Topol, A. ; Sheraw, C. ; Wong, Kai-Kit ; Shao, Xingyue ; Knarr, R. ; Rossnagel, S. ; Yang, C.-C. ; Baker-O´Neal, B. ; Simon, A. ; Haran, B. ; Li, Yuhua ; Ouyang, Chunmei ; Allen, S. ; Brodsky, C. ; Cohen, Sholom ; Deligianni, L. ; Chen, Xia ; Deshpande, S
Author_Institution :
T.J. Watson Res. Center, IBM Semicond. R&D Center, Yorktown Height, NY
Abstract :
A key challenge for high performance CMOS devices is the external parasitic resistance. This paper addresses scaling trends of contact level and discusses emerging constraints related to the properties of materials used in the current technology. Experimental and theoretical data presented herein are critical in understanding CA challenges beyond the 45 nm technology node and show great potential for copper as the alternative to tungsten process for CA metallization
Keywords :
CMOS integrated circuits; integrated circuit metallisation; 45 nm; CA metallization; CMOS; contact level; external parasitic resistance; scaled metal contacts; scaling trends; silicide; CMOS technology; Contact resistance; Copper; Metallization; Nanoscale devices; Plugs; Predictive models; Research and development; Silicides; Tungsten;
