Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)

Author

Thean, Aaron Voon-Yew ; Zhang, Dejing ; Vartanian, V. ; Adams, V. ; Conner, J. ; Canonico, Massimo ; Desjardin, H. ; Grudowski, P. ; Gu, Bin ; Shi, Z.-H. ; Murphy, Sinead ; Spencer, G. ; Filipiak, S. ; Goedeke, D. ; Wang, X.-D. ; Goolsby, B. ; Dhandapani,

Author_Institution

Freescale Semicond. Inc., Austin, TX

fYear

0

fDate

0-0 0

Firstpage

130

Lastpage

131

Abstract

This paper describes a biaxial-uniaxial hybridized strained CMOS technology achieved through selective uniaxial relaxation of thick SSOI, dual-stress nitride capping layer, and embedded SiGe source/drain. Through novel strain engineering, nFET/pFET Idsat enhancements as high as 27%/36% have been achieved for sub-40nm devices at 1V with 30% reduction in gate leakage current, while introducing minimum process complexity. This work demonstrates the scalability of SC-SSOI and its advantages over pure biaxial and single uniaxial strained Si technologies

Keywords

CMOS integrated circuits; Ge-Si alloys; MOSFET; relaxation; silicon; silicon-on-insulator; substrates; 1 V; SC-SSOI; SiGe; biaxial-uniaxial hybridized CMOS technology; dual-stress nitride capping layer; gate leakage current; process-substrate stress hybridization; selective uniaxial relaxation; strain engineering; strain-enhanced CMOS; strained CMOS technology; super-critically thick strained silicon directly on insulator; CMOS process; CMOS technology; Capacitive sensors; Germanium silicon alloys; Insulation; Leakage current; Scalability; Silicon germanium; Silicon on insulator technology; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705251

Filename

1705251