F2: 3D stacking technologies for image sensors and memories

Three-dimensional (3D) stacking integration is offering many product benefits to SoC and memory: performance enhancements, product miniaturization and cost reduction. Besides, image sensors featuring 3D stacking of a specialized image sensor layer on the top of a deep submicron digital CMOS have just come to the market. The objective of this forum is to present applications and details of process integration, device techniques, circuits and system featuring 3D stacking integration. This will start with an overview of 3D stacking ICs, followed by a system perspective with scaling the memory wall. The next two talks will discuss challanges for power reduction with wide memory bandwidth, and performance gains through advanced packaging and chip stacking. This is followed by two talks covering challenges for foundry-specific issues and impact on device performance. The last two talks highlight how to integrate an imaging device on an SoC layer: technical issues and phenomenon of 3D stacked image sensor products, and evolution of 3D integration for imaging systems.