DocumentCode
262608
Title
Dynamic Virtual Channel Configuration for Efficient Multicore Systems
Author
Gharan, Masoud Oveis ; Khan, Gul N.
Author_Institution
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada
fYear
2014
fDate
2-4 July 2014
Firstpage
445
Lastpage
450
Abstract
With the growing number of on-chip cores in multicore systems, there is an urgent need of efficient communication structures. NoC (Network-on-Chip) plays an important role in determining the performance of on-chip communication for multicore systems. Specifically, packet-based wormhole communication is known as the most viable solution for an MPSoC involving NoCs. In NoC design, the buffer organization facilitates the use of Virtual Channels (VC). Formally, a VC organization can be categorized into two types: static and dynamic. In dynamic and adaptive VC organization, variable number of buffer slots is used for VCs depending on the real-time on-chip traffic conditions. In this context, we introduce a new dynamic scheme for Efficient Virtual Channel organization (EVC), where a VC is reserved when a message packet enters the router and released when the packet leaves the router. This prevents a VC to hold more than one packet that subsequently removes the blocking of other packets. Our proposed technique can be implemented by amending the previously introduced dynamically allocated multi-queue schemes. In these schemes, an input or output port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to real-time traffic. The simulation results support the advantages of our proposed EVC methodology and the experimental results confirm that our approach improves network latency and throughput as compared to conventional VC based multicore system designs.
Keywords
multiprocessing systems; network-on-chip; queueing theory; EVC; NoC; efficient virtual channel configuration; multicore systems; multiqueue scheme; network-on-chip; Hardware; Multicore processing; Organizations; Ports (Computers); System-on-chip; Throughput; Traffic control; Head-of-Line blocking; Multicore Systems; NoC; dynamic virtual channels; efficient on-chip communication;
fLanguage
English
Publisher
ieee
Conference_Titel
Complex, Intelligent and Software Intensive Systems (CISIS), 2014 Eighth International Conference on
Conference_Location
Birmingham
Print_ISBN
978-1-4799-4326-5
Type
conf
DOI
10.1109/CISIS.2014.63
Filename
6915554
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