High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology

Author

Yamaguchi, S. ; Tai, K. ; Hirano, T. ; Ando, T. ; Hiyama, S. ; Wang, J. ; Hagimoto, Y. ; Nagahama, Y. ; Kato, T. ; Nagano, K. ; Yamanaka, M. ; Terauchi, S. ; Kanda, S. ; Yamamoto, R. ; Tateshita, Y. ; Tagawa, Y. ; Iwamoto, H. ; Saito, M. ; Nagashima, N. ;

Author_Institution

Semicond. Technol. Dev. Group, Sony Corp., Kanagawa

fYear

0

fDate

0-0 0

Firstpage

152

Lastpage

153

Abstract

We have developed a dual metal gate CMOS technology with HfSi_x for nMOS and Ru for pMOS on HfO₂ gate dielectric. These gate stacks show high mobility (100% of universal mobility for electron, 80% for hole at high fields) down to T_inv of 1.7 nm and symmetrical low V_t equivalent to poly-Si/SiO₂. As a result, high drive currents of 780 muA/mum and 265 muA/mum at I_off = 1 nA/mum are achieved for V_dd = 1.0 V in L_g = 60 nm nMOS and pMOS, respectively We have applied the mobility enhancement technology to the Ru/HfO₂ pMOS by utilizing (110)-substrate. As a result, an excellent drive current of 400 muA/mum (151% improvement over (100)-p⁺poly-Si/SiO₂) is achieved

Keywords

CMOS integrated circuits; carrier mobility; hafnium compounds; high-k dielectric thin films; low-power electronics; ruthenium; silicon compounds; substrates; (100) substrate; 1 V; 60 nm; HfSi; Ru-HfO₂; Si-SiO₂; bulk CMOS technology; drive current; dual metal gate CMOS; gate dielectric; high field mobility; low threshold voltage; mobility enhancement; nMOS; pMOS; universal mobility; CMOS process; CMOS technology; Charge carrier processes; Electrodes; Electron mobility; Hafnium oxide; High-K gate dielectrics; MOS devices; Threshold voltage; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705262

Filename

1705262