Title :
55nm CMOS Technology for Low Standby Power/Generic Applications Deploying the Combination of Gate Work Function Control by HfSiON and Stress-Induced Mobility Enhancement
Author :
Nakamura, H. ; Nakahara, Y. ; Kimizuka, N. ; Abe, T. ; Yamamoto, I. ; Fukase, T. ; Nakayama, T. ; Taniguchi, K. ; Masuzaki, K. ; Uejima, K. ; Iwamoto, T. ; Tatsumi, T. ; Imai, K.
Author_Institution :
Syst. Devices Res. Labs., NEC Corp., Kanagawa
Abstract :
A 55nm node low standby power/generic CMOS technology is demonstrated. The transistor deploys the combination of high-k gate dielectric film and process-induced stress technologies. It features high drive currents with low leakage, wide coverage of transistor performance and process simplicity. Ion of 525/295 muA/mum at Ion of 20 muA/mum and Ion of 780/400 muA/mum at Ioff of 3 nA/mum with supply voltage of 1.2 V have been achieved. A leading-edge ArF immersion lithography has been utilized for fine-pitch design rules such as L/S of 160 nm for metal 1 layer. A 0.432 mum2 SRAM cell shows a sufficient SNM of 130 mV at supply voltage of 0.8 V
Keywords :
CMOS integrated circuits; SRAM chips; argon compounds; carrier mobility; fine-pitch technology; hafnium compounds; high-k dielectric thin films; immersion lithography; nanotechnology; silicon compounds; work function; 0.8 V; 1.2 V; 130 mV; 160 nm; 55 nm; CMOS technology; HfSiON; SRAM; fine-pitch design rules; gate work function control; high-k gate dielectric film; immersion lithography; low standby power; process-induced stress; stress-induced mobility enhancement; CMOS process; CMOS technology; Degradation; Impurities; Lithography; National electric code; Process control; Random access memory; Stress control; Voltage control;
Conference_Titel :
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0005-8
DOI :
10.1109/VLSIT.2006.1705265
