Title :
RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology
Author :
Ahsan, Ishtiaq ; Zamdmer ; Glushchenkov, O. ; Logan, R. ; Nowak, Edward J. ; Kimura, Hiromitsu ; Zimmerman, Jeramy ; Berg, Guy ; Herman, Jakub ; Maciejewski, E. ; Chan, Alvin ; Azuma, A. ; Deshpande, S. ; Dirahoui, B. ; Freeman, G. ; Gabor, Attila ; Gribe
Author_Institution :
IBM Syst. & Technol. Group, Hopewell Junction, NY
Abstract :
We report, for the first time, a detailed study of intra-die variation (IDV) of CMOS inverter delay for the 65nm technology, driven by mm-scale variations of rapid thermal annealing (RTA). We find that variation in VT and REXT accounts for most of the IDV in delay and leakage and is modulated by lamp RTA ramp rate. We show a good correlation of inverter delay to mm-scale variation in the predicted reflectivity of the device pattern densities
Keywords :
CMOS logic circuits; delays; logic gates; nanotechnology; rapid thermal annealing; 65 nm; CMOS inverter delay; RTA; anneal ramp rate; device pattern density; intra-die variations; parametric sensitivities; rapid thermal annealing; stage delay; CMOS technology; Delay effects; Electric variables measurement; FETs; Inverters; Length measurement; Ring oscillators; Testing; Thermal conductivity; Very large scale integration;
Conference_Titel :
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0005-8
DOI :
10.1109/VLSIT.2006.1705271
