• DocumentCode
    262642
  • Title

    Session 15 overview: Digital PLLs: High-performance digital subcommittee

  • Author

    Hill, Anthony ; Hayashi, Hiroo

  • Author_Institution
    Texas Instruments, Dallas, TX
  • fYear
    2014
  • fDate
    9-13 Feb. 2014
  • Firstpage
    264
  • Lastpage
    265
  • Abstract
    The four papers presented in this session highlight developments in clock generation and distribution. These papers demonstrate the growing trend toward fully-synthesizable digital PLLs. Solutions presented relate to digital PLL integration, including power-supply noise rejection, temperature compensation, and fast frequency switching required in modern SoCs.
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4799-0918-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.2014.6757561
  • Filename
    6757561
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=262642